Decode the instruction and write a complete mips Health

decode the instruction and write a complete mips

Introduction to the MIPS Processor University of Notre Dame! CSE 30321 – Lecture 10 – The MIPS Datapath! Single Cycle Implementation! •! Each instruction takes one cycle to complete.!

MIPS Pipeline cs.cornell.edu

10a MIPS Datapath University of Notre Dame. As you have seen in class and in the readings from Patterson and Hennessy, MIPS machine instructions are encoded as 32-bit values. Each 32-bit value representing an instruction is viewed as a collection of fields that determine the instruction's operation and its operands., As you have seen in class and in the readings from Patterson and Hennessy, MIPS machine instructions are encoded as 32-bit values. Each 32-bit value representing an instruction is viewed as a collection of fields that determine the instruction's operation and its operands..

MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 Introduction to the R10000 Processor 3 1.2 What is a Superscalar Processor? A superscalar processor is one that can fetch, execute and complete more than one instruction in parallel. Pipeline and Superpipeline Architecture A MIPS Computer Simulator Applet Fetch, Decode, Execute, Memory and Write Back. Each shows the address of the instruction they are working on and other pertinant information. If the number is larger than the number of steps needed to complete the program the program will terminate when the first non-instruction is executed.

Instruction Fetch Instruction Decode/Register fetch Execute/ Address Calculation Memory Access Write Back This pipeline has five stages. Each stage should take one cycle. While the IF is fetching an instruction then Decode is decoding the previous instruction; and execute is doing the one before. No pipeline –time for 1 instruction is k cycles. CS61CFall%2013–%4–%Everything%isa%Number!%! Decoding)MIPS)Instructions)) Every!MIPs!instructionis!representedwith32bits!!They!come!inthree!formats:!

• Instruction lookahead capability—fetch, decode and issue instructions beyond the current instruction • Instruction-completion—complete execution • Processor lookahead capability—complete issued instructions beyond the current instruction • Instruction-commit—write back results to the RegFile or D$ (i.e., change the machine state) For a homework assignment I've been given the task of parsing out information from an 32-bit MIPS instruction. (For more information on the instruction formats, see here).The instructor has provided us with a header file enumerating all of the functions required, and it's my job to implement them.

instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) – multiplexors (mux) needed at the input of shared elements with control lines to do the selection – write signals to control writing to the Register File and Data Memory • Cycle time is determined by length of the longest path MIPS Instructions Note: You can have this handout on both exams. Instruction Formats: Instruction formats: all 32 bits wide (one word): 6 5 5 5 5 6

But there's certainly no way the instruction above could be translated into a 32-bit machine instruction, since the immediate value alone would require 32 bits. This is an example of a pseudo-instruction. A MIPS assembler, or SPIM, may be designed to support such extensions that make it easier to write complex programs. 5 cycle instruction forwarding - MIPS. Ask Question Asked 2 years, 4 months ago. Careful design of the logic ensures that IF/ID/WB are "complete" in less than half a clock cycle. In a simulator, you simply have to update the register file from writeback before decode is executed. if I write to decode early,

You do not decode x86 like you decode mips or arm or others that are designed differently. All of them have a decode that says look at these bits and determine the instruction or determine if I need more bits, but x86 does it one way, mips does it another, arm does it another. There are pros and cons to each. You do not decode x86 like you decode mips or arm or others that are designed differently. All of them have a decode that says look at these bits and determine the instruction or determine if I need more bits, but x86 does it one way, mips does it another, arm does it another. There are pros and cons to each.

Apr 15, 2010В В· the execution of an instruction. (Example: The instruction word fetched in stage 1 determines the destination of the register write in stage 5. The ALU result for an address computation in stage 3 is needed as the memory address for lw or sw in stage 4.) These outputs must be stored in intermediate registers for future use. Apr 15, 2010В В· the execution of an instruction. (Example: The instruction word fetched in stage 1 determines the destination of the register write in stage 5. The ALU result for an address computation in stage 3 is needed as the memory address for lw or sw in stage 4.) These outputs must be stored in intermediate registers for future use.

instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) – multiplexors (mux) needed at the input of shared elements with control lines to do the selection – write signals to control writing to the Register File and Data Memory • Cycle time is determined by length of the longest path MIPS Pipeline ! Five stages, one step per stage 1. IF: Instruction fetch from memory Few and regular instruction formats ! Can decode and read registers in one step ! Need to wait for previous instruction to complete its data read/write ! Control hazard ! Deciding on control action depends on

CoE/ECE 0142 Computer Organization Pipelining Instructor: Jun Yang Slides are adapted from Zilles Executing a MIPS instruction can take up to five steps. We shouldn’t have to wait for the entire instruction to complete before Nov 13, 2018 · MIPS Assembly/Instruction Formats. From Wikibooks, open books for an open world < MIPS Assembly. The latest reviewed version was checked on 13 November 2018. There are 17 pending changes awaiting review. Jump to navigation Jump to search. MIPS Assembly.

CoE/ECE 0142 Computer Organization Pipelining Instructor: Jun Yang Slides are adapted from Zilles Executing a MIPS instruction can take up to five steps. We shouldn’t have to wait for the entire instruction to complete before Sep 16, 2013 · MIPS register instruction decoding. Ask Question 0. I've decode the three MIPS registries under here, but I'm not sure if I'm applying the theory correctly. Could someone confirm my answers and perhaps shed some light on decoding the first address? How can one write good dialogue in a story without sounding wooden? How to turn off

16 bit Reduced Instruction Set Computer UIC Engineering

decode the instruction and write a complete mips

EECS150 Digital Design Lecture 7- MIPS CPU Microarchitecture. MIPS Instruction Decoding Due: March 17, 11:59pm Please note! This portion of your assignment is the first part of a two-part sequence. You should plan to use the code you write for this assignment to complete the next part of this sequence. Please start early and make sure that you have a complete working assignment to hand-in., • Instruction lookahead capability—fetch, decode and issue instructions beyond the current instruction • Instruction-completion—complete execution • Processor lookahead capability—complete issued instructions beyond the current instruction • Instruction-commit—write back results to the RegFile or D$ (i.e., change the machine state).

Encoding & Decoding MIPS Assembly Language Programming

decode the instruction and write a complete mips

Translate C into MIPS assembly TU/e. MIPS Pipeline ! Five stages, one step per stage 1. IF: Instruction fetch from memory Few and regular instruction formats ! Can decode and read registers in one step ! Need to wait for previous instruction to complete its data read/write ! Control hazard ! Deciding on control action depends on May 17, 2017В В· When I was learning about pipelined MIPS processors we split the processor into a few different stages: Instruction Fetch, Instruction Decode, Execution, Memory, and Write Back. Below is a standard looking MIPS processor In the above image each st....

decode the instruction and write a complete mips


Assignment 4 Solutions Pipelining and Hazards Alice Liang May 3, 2013 1 Processor Performance The critical path latencies for the 7 major blocks in a simple processor are given below. May 17, 2017В В· When I was learning about pipelined MIPS processors we split the processor into a few different stages: Instruction Fetch, Instruction Decode, Execution, Memory, and Write Back. Below is a standard looking MIPS processor In the above image each st...

May 17, 2017В В· When I was learning about pipelined MIPS processors we split the processor into a few different stages: Instruction Fetch, Instruction Decode, Execution, Memory, and Write Back. Below is a standard looking MIPS processor In the above image each st... 16 bit Reduced Instruction Set Computer (RISC) Processor Design A Project Report wait for one instruction to complete before starting the next. instruction decode, instruction execute, memory and input output addressing and write-back to memory. These stages are executed in parallel which implies that as soon as one stage

Write‐ Memory Back Instruction Fetch Execute Instruction Decode register file control A Processor “RISC” load‐store architecture 1.Instruction fetch (IF) –get instruction from memory, increment PC 2.Instruction Decode (ID) –translate opcodeinto control signals and read registers MIPS Instruction Types Arithmetic/Logical Assignment 4 Solutions Pipelining and Hazards Alice Liang May 3, 2013 1 Processor Performance The critical path latencies for the 7 major blocks in a simple processor are given below.

MIPS AL Supplement - Page 1. The main RISC philosophy (mid-80’s and after) is to design the assembly language (AL) to optimize the One possible break down of an instruction execution into stages would be: Write-back ALU or load instruction: write result into register file write register value from Decode stage to memory at effective Part 1: Decode, instructions.txt, and test cases - Due 9/17/10. For this first submission deadline, there are three required components. You must complete the Decode function in computer.c so that it works for each of the instructions listed above.

MIPS AL Supplement - Page 1. The main RISC philosophy (mid-80’s and after) is to design the assembly language (AL) to optimize the One possible break down of an instruction execution into stages would be: Write-back ALU or load instruction: write result into register file write register value from Decode stage to memory at effective Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS. Note: some of the details are intentionally omitted. You must use what you have learned throughout the semester to complete the project.

Lecture 7- MIPS CPU Microarchitecture Feb 4, 2012 John Wawrzynek 1. each instruction to complete all stages without interruption and within one cycle. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 14. Spring 2012 EECS150 - Lec07-MIPS Page MIPS Processor (Multiple Cycle) To overcome these weaknesses, we now consider multiple-cycle processor: The hardware compoments: Break Instruction Execution into Steps. Each instruction is executed in several steps (each taking one clock cycle), and the operations in each step are called microoperations (-operations).

MIPS AL Supplement - Page 1. The main RISC philosophy (mid-80’s and after) is to design the assembly language (AL) to optimize the One possible break down of an instruction execution into stages would be: Write-back ALU or load instruction: write result into register file write register value from Decode stage to memory at effective MIPS Instruction Reference. This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly language syntax supported by the MIPS assembler. Hyphens in the encoding indicate "don't care" bits which are not considered when an instruction is

You do not decode x86 like you decode mips or arm or others that are designed differently. All of them have a decode that says look at these bits and determine the instruction or determine if I need more bits, but x86 does it one way, mips does it another, arm does it another. There are pros and cons to each. 1. fetch the next instruction from memory 2. decode the instruction 3. execute the instruction Decode determines: operation to execute read/write 12/24. In MIPS, each instruction is exactly 32-bits long What is the address of the next instruction?

Lecture 7- MIPS CPU Microarchitecture Feb 4, 2012 John Wawrzynek 1. each instruction to complete all stages without interruption and within one cycle. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 14. Spring 2012 EECS150 - Lec07-MIPS Page Question: Decode 0x2000402A As A MIPS Assembly Language Instruction. Show Your Work In The Larger Box. Write The Complete Instruction, Including Operands, In The Smaller Box Below. (Use Register Name(s), Not Numbers.)

What is MIPS, MIPS Instruction, MIPS Implementation MIPS is implementation of a RISC architecture An arithmetic-logical or load instruction must write the data from the ALU or memory back into a register. Lastly, for a branch instruction, we may need to change the next instruction address Instruction decode/register file read: As in the MIPS Instruction Decoding Due: March 17, 11:59pm Please note! This portion of your assignment is the first part of a two-part sequence. You should plan to use the code you write for this assignment to complete the next part of this sequence. Please start early and make sure that you have a complete working assignment to hand-in.

Write a mips program that reads a string from user input

decode the instruction and write a complete mips

A MIPS Computer Simulator Applet Valley City State. What is MIPS, MIPS Instruction, MIPS Implementation MIPS is implementation of a RISC architecture An arithmetic-logical or load instruction must write the data from the ALU or memory back into a register. Lastly, for a branch instruction, we may need to change the next instruction address Instruction decode/register file read: As in the, Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS. Note: some of the details are intentionally omitted. You must use what you have learned throughout the semester to complete the project..

MIPS Assembly Language Supplement (Section 4.14 of the

IF and ID Stages Simple MIPS Instruction Formats. Lecture 7- MIPS CPU Microarchitecture Feb 4, 2012 John Wawrzynek 1. each instruction to complete all stages without interruption and within one cycle. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 14. Spring 2012 EECS150 - Lec07-MIPS Page, Now that we have a complete datapathfor R-format instructions, let’s add in support for I-format instructions. In our limited MIPS instruction set, these are lw, sw, and beq. •The opfield is used to identify the type of instruction. •The rsfield is the source register..

As you have seen in class and in the readings from Patterson and Hennessy, MIPS machine instructions are encoded as 32-bit values. Each 32-bit value representing an instruction is viewed as a collection of fields that determine the instruction's operation and its operands. MIPS Instructions Note: You can have this handout on both exams. Instruction Formats: Instruction formats: all 32 bits wide (one word): 6 5 5 5 5 6

Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS. Note: some of the details are intentionally omitted. You must use what you have learned throughout the semester to complete the project. Assembly Language Assignment Help, Write a mips program that reads a string from user input, Description Write a MIPS program that reads a string from user input, reverse each word (defined as a sequence of English alphabetic letters or numeric digits without any punctuations) in the string, and prints the string with the reversed words o

CoE/ECE 0142 Computer Organization Pipelining Instructor: Jun Yang Slides are adapted from Zilles Executing a MIPS instruction can take up to five steps. We shouldn’t have to wait for the entire instruction to complete before MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 Introduction to the R10000 Processor 3 1.2 What is a Superscalar Processor? A superscalar processor is one that can fetch, execute and complete more than one instruction in parallel. Pipeline and Superpipeline Architecture

MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 Introduction to the R10000 Processor 3 1.2 What is a Superscalar Processor? A superscalar processor is one that can fetch, execute and complete more than one instruction in parallel. Pipeline and Superpipeline Architecture Lecture 7- MIPS CPU Microarchitecture Feb 4, 2012 John Wawrzynek 1. each instruction to complete all stages without interruption and within one cycle. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 14. Spring 2012 EECS150 - Lec07-MIPS Page

But there's certainly no way the instruction above could be translated into a 32-bit machine instruction, since the immediate value alone would require 32 bits. This is an example of a pseudo-instruction. A MIPS assembler, or SPIM, may be designed to support such extensions that make it easier to write complex programs. MIPS machine language is designed to be easy to decode. —Each MIPS instruction is the same length, 32 bits. —There are only three different instruction formats, which are very similar to each other. Studying MIPS machine language will also reveal some restrictions in the instruction set architecture, and how they can be overcome.

MIPS R10000 Microprocessor User's Manual Version 2.0 of October 10, 1996 Introduction to the R10000 Processor 3 1.2 What is a Superscalar Processor? A superscalar processor is one that can fetch, execute and complete more than one instruction in parallel. Pipeline and Superpipeline Architecture 1. fetch the next instruction from memory 2. decode the instruction 3. execute the instruction Decode determines: operation to execute read/write 12/24. In MIPS, each instruction is exactly 32-bits long What is the address of the next instruction?

MIPS Processor (Multiple Cycle) To overcome these weaknesses, we now consider multiple-cycle processor: The hardware compoments: Break Instruction Execution into Steps. Each instruction is executed in several steps (each taking one clock cycle), and the operations in each step are called microoperations (-operations). Quiz for Chapter 4 The Processor 3.10 WB MIPS design. For the above code, complete the pipeline diagram below (instructions on the left, cycles on top) for the code. Insert the characters IF, ID, EX, MEM, WB for each instruction in the boxes. Assume that there two levels of bypassing, that variation in the MIPS instruction set and the

instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) – multiplexors (mux) needed at the input of shared elements with control lines to do the selection – write signals to control writing to the Register File and Data Memory • Cycle time is determined by length of the longest path 5 cycle instruction forwarding - MIPS. Ask Question Asked 2 years, 4 months ago. Careful design of the logic ensures that IF/ID/WB are "complete" in less than half a clock cycle. In a simulator, you simply have to update the register file from writeback before decode is executed. if I write to decode early,

° Successor instruction – jumps, conditions, branches - fetch-decode-execute is implicit! 6 1998 Morgan Kaufmann Publishers MIPS Design Principles • Reduced Instruction Set Computers (RISC) design philosophy • Principles guiding Instruction Set Design – Smaller is faster • Example: Only 32 registers in MIPS – Simplicity favors Chapter 4 — The Processor — 7 Pipelining and ISA Design MIPS ISA designed for pipelining All instructions are 32-bits Easier to fetch and decode in one cycle c.f. x86: 1- to 17-byte instructions Few and regular instruction formats Can decode and read registers in one step Load/store addressing

° Successor instruction – jumps, conditions, branches - fetch-decode-execute is implicit! 6 1998 Morgan Kaufmann Publishers MIPS Design Principles • Reduced Instruction Set Computers (RISC) design philosophy • Principles guiding Instruction Set Design – Smaller is faster • Example: Only 32 registers in MIPS – Simplicity favors Lecture 7- MIPS CPU Microarchitecture Feb 4, 2012 John Wawrzynek 1. each instruction to complete all stages without interruption and within one cycle. 1. Instruction Fetch 2. Decode/ Register Read 3. Execute 4. Memory 5. Reg. Write 14. Spring 2012 EECS150 - Lec07-MIPS Page

MIPS Instruction Reference uidaho.edu

decode the instruction and write a complete mips

MIPS Pipe Line. • Instruction lookahead capability—fetch, decode and issue instructions beyond the current instruction • Instruction-completion—complete execution • Processor lookahead capability—complete issued instructions beyond the current instruction • Instruction-commit—write back results to the RegFile or D$ (i.e., change the machine state), MIPS Instruction Decoding Due: March 17, 11:59pm Please note! This portion of your assignment is the first part of a two-part sequence. You should plan to use the code you write for this assignment to complete the next part of this sequence. Please start early and make sure that you have a complete working assignment to hand-in..

Lecture 4 Instruction Level Parallelism (2). You do not decode x86 like you decode mips or arm or others that are designed differently. All of them have a decode that says look at these bits and determine the instruction or determine if I need more bits, but x86 does it one way, mips does it another, arm does it another. There are pros and cons to each., CoE/ECE 0142 Computer Organization Pipelining Instructor: Jun Yang Slides are adapted from Zilles Executing a MIPS instruction can take up to five steps. We shouldn’t have to wait for the entire instruction to complete before.

LECTURE 5 Single-Cycle Datapathand Control

decode the instruction and write a complete mips

MIPS Hello World MIPS Assembly 1 Virginia Tech. MIPS Instruction Reference. This is a description of the MIPS instruction set, their meanings, syntax, semantics, and bit encodings. The syntax given for each instruction refers to the assembly language syntax supported by the MIPS assembler. Hyphens in the encoding indicate "don't care" bits which are not considered when an instruction is Question: Decode 0x2000402A As A MIPS Assembly Language Instruction. Show Your Work In The Larger Box. Write The Complete Instruction, Including Operands, In The Smaller Box Below. (Use Register Name(s), Not Numbers.).

decode the instruction and write a complete mips


You do not decode x86 like you decode mips or arm or others that are designed differently. All of them have a decode that says look at these bits and determine the instruction or determine if I need more bits, but x86 does it one way, mips does it another, arm does it another. There are pros and cons to each. Final Project: MIPS-like Microprocessor Objective: The objective of this project is to design, simulate, and implement a simple 32-bit microprocessor with an instruction set that is similar to a MIPS. Note: some of the details are intentionally omitted. You must use what you have learned throughout the semester to complete the project.

In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor, which is widely used by many universities in academic courses related to computer organization and architecture. MIPS Processor (Multiple Cycle) To overcome these weaknesses, we now consider multiple-cycle processor: The hardware compoments: Break Instruction Execution into Steps. Each instruction is executed in several steps (each taking one clock cycle), and the operations in each step are called microoperations (-operations).

CS61CFall%2013–%4–%Everything%isa%Number!%! Decoding)MIPS)Instructions)) Every!MIPs!instructionis!representedwith32bits!!They!come!inthree!formats:! May 17, 2017 · When I was learning about pipelined MIPS processors we split the processor into a few different stages: Instruction Fetch, Instruction Decode, Execution, Memory, and Write Back. Below is a standard looking MIPS processor In the above image each st...

Apr 15, 2010В В· the execution of an instruction. (Example: The instruction word fetched in stage 1 determines the destination of the register write in stage 5. The ALU result for an address computation in stage 3 is needed as the memory address for lw or sw in stage 4.) These outputs must be stored in intermediate registers for future use. In this project, a 16-bit single-cycle MIPS processor is implemented in Verilog HDL. MIPS is an RISC processor, which is widely used by many universities in academic courses related to computer organization and architecture.

Instruction decode and Control ALU Unit M D R M A R Instruction [31-0] Write MemWr MemRd Data memory Instruction memory 191. TheMIPS instructionset: Following is the MIPS instruction format: op rs rt rd shamt funct 31 2026 25 21 1516 11 10 6 5 0 I-type (immediate) op rs rt 31 2026 25 21 1516 0 immediate R-type (register) For a homework assignment I've been given the task of parsing out information from an 32-bit MIPS instruction. (For more information on the instruction formats, see here).The instructor has provided us with a header file enumerating all of the functions required, and it's my job to implement them.

1. fetch the next instruction from memory 2. decode the instruction 3. execute the instruction Decode determines: operation to execute read/write 12/24. In MIPS, each instruction is exactly 32-bits long What is the address of the next instruction? Nov 13, 2018В В· MIPS Assembly/Instruction Formats. From Wikibooks, open books for an open world < MIPS Assembly. The latest reviewed version was checked on 13 November 2018. There are 17 pending changes awaiting review. Jump to navigation Jump to search. MIPS Assembly.

Topics of today Final lecture of first semester Recap of MIPS instruction set and formats MIPS addressing modes Rit ll tiRegister allocation graph coloring sppgilling Translating C statements into Assembler if statement hl MIPS_3000 while statement switch statement procedure / function (leaf and non-leaf) @HC Computation 5JJ70 pg 3 p Assembly Language Assignment Help, Write a mips program that reads a string from user input, Description Write a MIPS program that reads a string from user input, reverse each word (defined as a sequence of English alphabetic letters or numeric digits without any punctuations) in the string, and prints the string with the reversed words o

CS61CFall%2013–%4–%Everything%isa%Number!%! Decoding)MIPS)Instructions)) Every!MIPs!instructionis!representedwith32bits!!They!come!inthree!formats:! Assembly Language Assignment Help, Write a mips program that reads a string from user input, Description Write a MIPS program that reads a string from user input, reverse each word (defined as a sequence of English alphabetic letters or numeric digits without any punctuations) in the string, and prints the string with the reversed words o

•MIPS ISA designed for pipelining –All instructions are 32-bits •Easier to fetch and decode in one cycle •c.f. x86: 1- to 17-byte instructions –Few and regular instruction formats •Can decode and read registers in one step –Load/store addressing •Can calculate address in 3rd stage, access memory in 4th stage MIPS machine language is designed to be easy to decode. —Each MIPS instruction is the same length, 32 bits. —There are only three different instruction formats, which are very similar to each other. Studying MIPS machine language will also reveal some restrictions in the instruction set architecture, and how they can be overcome.

16 bit Reduced Instruction Set Computer (RISC) Processor Design A Project Report wait for one instruction to complete before starting the next. instruction decode, instruction execute, memory and input output addressing and write-back to memory. These stages are executed in parallel which implies that as soon as one stage 1. fetch the next instruction from memory 2. decode the instruction 3. execute the instruction Decode determines: operation to execute read/write 12/24. In MIPS, each instruction is exactly 32-bits long What is the address of the next instruction?

Assignment 4 Solutions Pipelining and Hazards Alice Liang May 3, 2013 1 Processor Performance The critical path latencies for the 7 major blocks in a simple processor are given below. MIPS Instruction Decoding Due: March 17, 11:59pm Please note! This portion of your assignment is the first part of a two-part sequence. You should plan to use the code you write for this assignment to complete the next part of this sequence. Please start early and make sure that you have a complete working assignment to hand-in.